 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| t-sminto 4b3 t s econd gen. m odular i sdn nt ( o rdinary) pef 80902 version 1.1 data sheet, ds 1, nov. 2001 wired communications never stop thinking.
edition 2001-11-12 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications t-sminto 4b3 t s econd gen. m odular i sdn nt ( o rdinary) pef 80902 version 1.1 data sheet, ds 1, nov. 2001 never stop thinking. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 80902 revision history: 2001-11-12 ds 1 previous version: preliminary data sheet 06.01 page subjects (major changes since last revision) table 10 figure 12 chapter 2.3.7.4 additional c/i-command ltd chapter 4.2 input leakage current ain, bin: max. 30a chapter 4.4 reduced power consumption pef 80902 table of contents page data sheet 2001-11-12 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 not supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.1 specific pins and test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 iom?-2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 4b3t frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 maintenance channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.3 coding from binary to ternary data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.4 decoding from ternary to binary data . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.4.1 monitoring of code violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.5 scrambler / descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.6 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.7 state machine for activation and deactivation . . . . . . . . . . . . . . . . . . . 23 2.3.7.1 state machine notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.7.2 awake protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.7.3 nt state machine (iec-t / ntc-t compatible) . . . . . . . . . . . . . . . . 26 2.3.7.4 inputs to the u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.7.5 outputs of the u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.7.6 nt-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.1 line coding, frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.2 s/q channels, multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.3 data transfer between iom?-2 and s0 . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.4 loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5.1 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1 layer 1 activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.1 generation of 4b3t signal elements . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.2 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . . 45 3.1.3 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.4 deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pef 80902 table of contents page data sheet 2001-11-12 3.1.5 activation procedures with loopback #2 . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 layer 1 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.1 loopback no.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.1.1 complete loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.3 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.4 oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.5 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6.1 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6.3 undervoltage detection characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 appendix: differences between q- and t-smint?o . . . . . . . . . . . . . . . 68 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.2 led pin act . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2.1 u-interface conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2.2 u-transceiver state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.3 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 pef 80902 list of figures page data sheet 2001-11-12 figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3 application example t-smint?o: standard nt1 . . . . . . . . . . . . . . . . . 12 figure 4 iom ? -2 frame structure of the t-smint?o . . . . . . . . . . . . . . . . . . . . 14 figure 5 state diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6 awake procedure initiated by the lt . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7 awake procedure initiated by the nt. . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8 nt state machine (iec-t/ntc-t compatible). . . . . . . . . . . . . . . . . . . 26 figure 9 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10 frame structure at reference points s and t (itu i.430). . . . . . . . . . 34 figure 11 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 13 activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14 activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 15 deactivation (always initiated by lt) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 16 activation of loopback #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19 external circuitry u-transceiver with external hybrid . . . . . . . . . . . . . 51 figure 20 external circuitry s-interface transmitter . . . . . . . . . . . . . . . . . . . . . . 54 figure 21 external circuitry s-interface receiver . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 22 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 23 maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . . 60 figure 24 input/output waveform for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 25 iom?-2 interface - bit synchronization timing . . . . . . . . . . . . . . . . . . 62 figure 26 iom-2 interface - frame synchronization timing . . . . . . . . . . . . . . . . 62 figure 27 reset input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 28 undervoltage control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 29 ntc-q compatible state machine q-smint?o: 2b1q . . . . . . . . . . . . 70 figure 30 iec-t/ntc-t compatible state machine t-smint?o: 4b3t . . . . . . . . 71 figure 31 external circuitry q- and t-smint?o . . . . . . . . . . . . . . . . . . . . . . . . . 73 pef 80902 list of tables page data sheet 2001-11-12 table 1 nt products of the 2nd generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4 lp2i states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6 frame structure a for downstream transmission lt to nt . . . . . . . . 16 table 7 frame structure b for upstream transmission nt to lt. . . . . . . . . . . 18 table 8 mms 43 coding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9 4b3t decoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11 differences to the former nt-sm of the iec-t/ntc-t . . . . . . . . . . . . . 27 table 12 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13 active states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14 m symbol output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15 signal output on uk0 in state test . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16 c/i-code output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17 4b3t signal elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18 generation of the 4b3t signal elements. . . . . . . . . . . . . . . . . . . . . . . 43 table 19 s/t-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20 u-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 21 s-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 22 crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23 maximum input currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24 s-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 25 u-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27 reset input signal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 28 parameters of the uvd/por circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 29 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 31 related documents to the u-interface. . . . . . . . . . . . . . . . . . . . . . . . . 69 table 32 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 33 dimensions of external components. . . . . . . . . . . . . . . . . . . . . . . . . . 73 pef 80902 overview data sheet 1 2001-11-12 1 overview the peb 80902 (t-smint o) offers all nt1 features known from the peb 8090 [9] and can hence replace the latter in all nt1 applications. table 1 on page 1 summarizes the 2nd generation nt products. table 1 nt products of the 2nd generation pef 80902 pef 81902 pef 82902 t-smint ? o t-smint ? ix t-smint ? i package p-mqfp-44 p-mqfp-64 p-tqfp-64 p-mqfp-64 p-tqfp-64 register access no u+s+hdlc+ iom ?2 u+s+iom ?2 access via n.a parallel (or sci or iom ?2 ) parallel (or sci or iom ?2 ) mclk, watchdog timer, sds, bcl, d- channel arbitration, iom ?2 access and manipulation etc. provided no yes yes hdlc controller no yes no nt1 mode available yes (only) no no pef 80902 overview data sheet 2 2001-11-12 1.1 references [1] ts 102 080, transmission and multiplexing; isdn basic rate access; digital transmission system on metallic local lines, etsi, november 1998 [2] ftz 1 tr 220 technische richtlinie, spezifikation der isdn schnittstelle uk0 schicht 1, deutsche telecom ag, august 1991 [3] ts 0284/96 technische spezifikation intelligenter netzabschlu? (int) mit den funktionen eines terminaladapters ta 2a/b (ohne internverkehr), deutsche telekom ag, m?rz 2001 [4] pr ets 300 012 draft, isdn; basic user network interface (uni), etsi, november 1996 [5] t1.605-1991, isdn-basic access interface for s and t reference points (layer 1 specification), ansi, 1991 [6] i.430, isdn user-network interfaces: layer 1 recommendations, itu, november 1988 [7] iec-t, isdn echocancellation circuit, peb 20901 (iec - td) / peb 20902 (iec - ta), preliminary target specification 11.88, siemens ag, 1988 [8] sbcx, s/t bus interface circuit extended, peb 2081 v3.4, user?s manual 11.96, siemens ag, 1996 [9] ntc-t, network termination controller (4b3t), peb 8090 v1.1, data sheet 06.98, siemens ag, 1998 [10] intc-q, intelligent network termination controller (2b1q), peb 8191 v1.1, data sheet 10.97, siemens ag, 1997 [11] q-sminto, 2b1 q s econd gen. m odular i sdn nt (o rdinary), pef 80912 q-smintix, 2b1 q s econd gen. m odular i sdn nt (i ntelligent e x ended), pef 81912 q-sminti, 2b1 q s econd gen. m odular i sdn nt (i ntelligent), pef 82912 v1.3, data sheets 03.01, infineon ag, 2001 [12] iom -2 interface reference guide, siemens ag, 03.91 [13] scout-s(x), siemens codec with s/t-transceiver, psb 2138x v1.1, preliminary data sheet 08.98, infineon technologies ag, 1999 [14] pita, pci interface for telephony/data applications v0.3, sican gmbh, september1997 [15] dual channel slicofi-2, hv-slic; duslic; peb3265, 4265, 4266; data sheet ds2, infineon technologies, july 2000. data sheet 3 2001-11-12 type package pef 80902 p-mqfp-44 4b3t second gen. modular isdn nt (ordinary) t-smint ? o pef 80902 version 1.1 cmos p-mqfp-44-2 1.2 features features known from the peb 8090 single chip solution including u- and s-transceiver perfectly suited for the nt1 in the isdn fully automatic activation and deactivation u-interface (4b3t) conform to etsi [1] and ftz [2]: ? meets all transmission requirements on all etsi and ftz loops with margin s/t-interface conform to etsi [4], ansi [5] and itu [6] ? supports point-to-point and bus configurations ? meets and exceeds all transmission requirements optional iom -2 interface eases chip testing and evaluation power-on reset and undervoltage detection with no external components esd robustness 2kv pef 80902 overview data sheet 4 2001-11-12 new features optional use of transformers with non-negligible resistance corresponding to up to 20 ? on the line sidepin vref and the according external capacitor removed inputs accept 3.3v and 5v i/o (open drain) accepts pull-up to 3.3v 1) pin compatible with q-smint o (2nd generation) leds indicating loopback 2 and activation status lowest power consumption due to ? low power cmos technology (0.35) ? newly optimized low power libraries ? high output swing on u- and s-line interface leads to minimized power consumption ? single 3.3 volt power supply 185mw (ntc-t: 233mw) power consumption with random data over etsi loop 2. 15mw typical power consumption in power down (as ntc-t; ntc-q: 28mw) 1.3 not supported are ... no integrated hybrid is provided by the t-smint o. therefore, an external hybrid is always required, which consists of only two additional resistors as compared to an integrated hybrid, but allows for more flexibility in board design. auxiliary iom ?2 interface sra (capacitive receiver coupling is not suited for s-feeding) nt-star with star point on the iom ? -2 bus (already not supported in ntc-t). 1) pull-ups to 5v must be avoided. a so-called ? hot-electron-effect ? would lead to long term degradation. pef 80902 overview data sheet 5 2001-11-12 1.4 pin configuration figure 1 pin configuration /vdddet /rsto vdda_sr vssa_sr xout xin bout vdda_ux vssa_ux aout fsc dcl bus vssd vddd tm2 tm1 /act 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 vssa_ur bin /rst dio vdda_ur dd du /lp2i sx1 tp1 vssa_sx vdda_sx sr1 sr2 sx2 ain t p 2 tm0 vssd vddd t-sminto pef 80902 pin_2.vsd pef 80902 overview data sheet 6 2001-11-12 1.5 block diagram figure 2 block diagram clock generation s-transceiver u-tansceiver por/uvd test modes iom-2 interface factory test xin xout aout bout ain bin tm1 tm0 sx2 sx1 sr2 sr1 led tp1 act bus dd du dcl fsc tm2 dio block diagram.vsd rst rsto vdddet tp2 lp2i s transceiver control pef 80902 overview data sheet 7 2001-11-12 1.6 pin definitions and functions table 2 pin definitions and functions pin symbol type function 2 vdda_ur ? supply voltage for u-receiver (3.3 v 5%) 1 vssa_ur ? analog ground (0 v) u-receiver 42 vdda_ux ? supply voltage for u-transmitter (3.3 v 5%) 43 vssa_ux ? analog ground (0 v) u-transmitter 36 vdda_sr ? supply voltage for s-receiver (3.3 v 5%) 37 vssa_sr ? analog ground (0 v) s-receiver 31 vdda_sx ? supply voltage for s-transmitter (3.3 v 5%) 30 vssa_sx ? analog ground (0 v) s-transmitter 19 vddd ? supply voltage digital circuits (3.3 v 5%) 20 vssd ? ground (0 v) digital circuits 8 vddd ? supply voltage digital circuits (3.3 v 5%) 9 vssd ? ground (0 v) digital circuits 22 fsc o frame sync: 8-khz frame synchronization signal 21 dcl o data clock: iom -2 interface clock signal (double clock): 512 khz 25 lp2i o loopback 2 indication: can directly drive a led (4ma). 0: loopback 2 closed 1: loopback 2 not closed. 23 dd i/o data downstream: data on the iom -2 interface pef 80902 overview data sheet 8 2001-11-12 24 du i/o data upstream: data on the iom -2 interface 7 dio i disable iom -2: 1: fsc, dcl, du and dd high z 0: fsc, dcl, du and dd push-pull 18 bus i (pu) bus mode on s-interface: 1: passive s-bus (fixed timing) 0: point-to-point / extended passive s-bus (adaptive timing) 5 rst i reset: low active reset input. schmitt-trigger input with hysteresis of typical 360mv. tie to ? 1 ? if not used. 6 rsto od reset output: low active reset output. 13 tm0 i test mode 0. selects test pattern (see page 10 ). 14 tm1 i test mode 1. selects test pattern (see page 10 ). 15 tm2 i test mode 2. selects test pattern (see page 10 ). 28 sx1 o s-bus transmitter output ( positive ) 29 sx2 o s-bus transmitter output ( negative ) 32 sr1 i s-bus receiver input 33 sr2 i s-bus receiver input 40 xin i crystal 1: connected to a 15.36 mhz crystal 39 xout o crystal 2: connected to a 15.36 mhz crystal table 2 pin definitions and functions (cont ? d) pin symbol type function pef 80902 overview data sheet 9 2001-11-12 pu: internal pull-up resistor (typ. 100a) i: input o: output (push-pull) od: output (open drain) 1.6.1 specific pins and test modes led pins act , lp2i a led can be connected to pin act to display four different states (off, slow flashing, fast flashing, on). it displays the activation status of the u- and s-transceiver according to table 3 . 44 aout o differential u-interface output 41 bout o differential u-interface output 3 ain i differential u-interface input 4 bin i differential u-interface input 34 vdddet i vdd detection: this pin selects if the v dd detection is active ( ? 0 ? ) and reset pulses are generated on pin rsto or whether it is deactivated ( ? 1 ? ) and an external reset has to be applied on pin rst. 12 act o activation led . indicates the activation status of u- and s- transceiver. can directly drive a led (4ma). 27 tp1 i test pin 1. used for factory device test. tie to ? v ss ? 35 tp2 i test pin 2. used for factory device test. tie to ? v ss ? 10,11, 16,17, 26,38 tie to ? 1 ? table 2 pin definitions and functions (cont ? d) pin symbol type function pef 80902 overview data sheet 10 2001-11-12 note: * denotes the duty cycle ?high? : ?low?. with: u_deactivated : ? deactivated state ? as defined in chapter 2.3.7.6 . u_activated : ? sbc synchronizing ? , ? wait for info u4h ? , and ? transparent ? as defined in chapter 2.3.7.6 . s-activated : ? activated state ? as defined in chapter 2.4.5.1 . note: optionally, pin act can drive a second led with inverse polarity (connect this additional led to 3.3v only). another led can be connected to pin lp2i to indicate an active loopback 2 according to table 4 . test modes different test patterns on the u- and s-interface can be generated via pins tm0-2 according to table 5 . table 3 act states pin act led u_deactivated u_activated s_activated v dd off 1 x x 2hz (1 : 1)* fast flashing 0 0 x 1hz (3 : 1)* slow flashing 0 1 0 gndon011 table 4 lp2i states pin lp2i led loopback 2 command in the c l -channel v dd off received no loopback 2 command or loopback deactivation after a loopback 2 command. gnd on loopback 2 command has been received. complete analog loop is being closed on the s-interface. table 5 test modes tm0 tm1 tm2 u-transceiver s-transceiver 0 0 0 reserved for future use. normal operation in this version. 001 0 1 0 normal operation 96 khz 1) continuous pulses 0 1 1 2 khz 2) single pulses pef 80902 overview data sheet 11 2001-11-12 1.7 system integration the t-smint o provides nt1 functionality without a microcontroller being necessary. special selections can be done via pin strapping (dio, bus, tm0-2). the device has no p interface. the iom -2 interface serves only for monitoring and debugging purposes. it can be regarded as a window to the internal iom -2. . 1 0 0 data through 3) normal operation 1 0 1 send single pulses 4) 1 1 0 quiet mode 5) 1 1 1 normal operation 1) the s-transceiver transmits pulses with alternating polarity at a rate of 192 khz resulting in a 96 khz envelope. 2) the s-transceiver transmits pulses with alternating polarity at a rate of 4 khz resulting in a 2 khz envelope. 3) forces the u-transceiver into the state ? transparent ? where it transmits signal u5. 4) forces the u-transceiver to go into state ? test ? and to send single pulses. the pulses are issued at 1.0 ms intervals and have a duration of 8.33 s. 5) the u-transceiver is hardware reset. table 5 test modes (cont ? d) tm0 tm1 tm2 u-transceiver s-transceiver pef 80902 overview data sheet 12 2001-11-12 figure 3 application example t-smint o: standard nt1 s u idcc peb2023 pin strap - mode selection iom-2 leds - loop 2 ind. - activation status u - interface s/t - interface nt1_appl.vsd - disable iom - 2 - p - to - p / bus selection - test pattern selection t-sminto pef80902 dc/dc-converter pef 80902 functional description data sheet 13 2001-11-12 2 functional description 2.1 reset generation external reset input at the rst input an external reset can be applied forcing the t-smint o in the reset state. this external reset signal is additionally fed to the rsto output. reset ouput if vdddet is active, then the deactivation of a reset output on rsto is delayed by t deact (see table 28 ). reset generation the t-smint o has an on-chip reset generator based on a power-on reset (por) and under voltage detection (uvd) circuit (see table 28 ). the por/uvd requires no external components. the por/uvd circuit can be disabled via pin vdddet . the requirements on v dd ramp-up during power-on reset are described in chapter 4.6.3 . clocks and data lines during reset during reset the data clock (dcl) and the frame synchronization (fsc) keep running. during reset dd and du are high; with the exception of: the output c/i code from the u-transceiver on dd is ? dr ? = 0000 the output c/i code from the s-transceiver on du is ? tim ? = 0000. pef 80902 functional description data sheet 14 2001-11-12 2.2 iom ? -2 interface the iom -2 interface always operates in nt mode according to the iom -2 reference guide [12]. 2.2.1 iom -2 functional description the iom -2 interface consists of four lines: fsc, dcl, dd, du. the rising edge of fsc indicates the start of an iom -2 frame. the dcl clock signal synchronizes the data transfer on both data lines du and dd. the dcl is twice the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle. note: it is not possible to write any data via iom -2 into the t-smint o. the iom -2 interface can be enabled/disabled with pin dio. the fsc signal is an 8 khz frame sync signal. the number of pcm timeslots on the transmit line is determined by the frequency of the dcl clock , with the 512 khz clock 1 channel consisting of 4 timeslots is available. iom ? -2 frame structure of the t-smint o the frame structure on the iom -2 data ports (du,dd) of the t-smint o with a dcl clock of 512 khz is shown in figure 4 . figure 4 iom ? -2 frame structure of the t-smint o the frame is composed of one channel: channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (not available in t-smint o) and a command/indication channel (ci0) for control of e.g. the u-transceiver. macro_19_qsminto pef 80902 functional description data sheet 15 2001-11-12 2.3 u-transceiver the statemachine of the u-transceiver is compatible to the nt state machine in the peb 8090 documentation [9], but includes some minor changes for simplification and compliance to ref. [1]. basic configurations are selected via pin strapping 2.3.1 4b3t frame structure the 4b3t u-interface performs full duplex data transmission and reception at the u- reference point according to etsi ts 102 080 and ftz 1tr 220. it applies the 4b3t block code together with adaptive echo cancelling and equalization. transmission performance shall be such, that it meets all etsi and ftz test loops with margin. the u-interface is designed for data transmission on twisted pair wires in local telephone loops, with basic access to isdn and a user bit rate of 144 kbit/s. the following information is transmitted over the twisted pair: bidirectional: ? b1, b2, d data channels ? 120 khz symbol clock ? 1 khz frame ? activation ? 1 kbit/s transparent channel (m symbol), (not implemented) from lt to nt side: ? power feeding ? deactivation ? remote control of test loops (m symbol) from nt to lt side: ? indication of monitored code violations (m symbol) performance requirements according to ftz 1 tr 220 (august 1991): on the u-interface, the following transmission ranges are achieved without additional signal regeneration on the loop (bit error rate 10 -7 ): with noise : 4.2 km on wires of 0.4 mm diameter and 8 km on 0.6 mm wires without noise : 5 km on wires of 0.4 mm diameter and 10 km on 0.6 mm wires note: typical attenuation of ftz wires of 0.4 mm diameter is about 7db/km in contrast to etsi wires of 0.4 mm with about 8db/km. the transmission ranges can be doubled by inserting a repeater for signal regeneration. performance requirements according to etsi ts 102 080 are met, too. 1 ms frames are transmitted via the u-interface, each consisting of: 108 symbols: 144 bit scrambled and coded b1 + b2 + d data pef 80902 functional description data sheet 16 2001-11-12 11 symbols: barker code for both symbol and frame synchronization (not scrambled) 1 symbol: ternary maintenance symbol (not scrambled) the 108 user data symbols are split into four equally structured groups. each group (27 ternary symbols, resp. 36 bits) contains the user data of two iom ? -2 frames in the same order (8b + 8b + 2d + 8b + 8b + 2d). different syncwords are used for each direction: downstream from lt to nt + + + ? ? ? + ? ? + ? upstream from nt to lt ? + ? ? + ? ? ? + + + on the nt side, the transmitted barker code begins 60 symbols after the received barker code and vice versa. table 6 frame structure a for downstream transmission lt to nt 123456789101112 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 13 14 15 16 17 18 19 20 21 22 23 24 d 1/2 d 1/2 d 1/2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 25 26 27 28 29 30 31 32 33 34 35 36 d 2 d 2 d 2 d 3 d 3 d 3 d 3 d 3 d 3 d 3 d 3 d 3 37 38 39 40 41 42 43 44 45 46 47 48 d 3 d 3 d 3 d 3/4 d 3/4 d 3/4 d 4 d 4 d 4 d 4 d 4 d 4 49 50 51 52 53 54 55 56 57 58 59 60 d 4 d 4 d 4 d 4 d 4 d 4 d 5 d 5 d 5 d 5 d 5 d 5 61 62 63 64 65 66 67 68 69 70 71 72 d 5 d 5 d 5 d 5 d 5 d 5 d 5/6 d 5/6 d 5/6 d 6 d 6 d 6 73 74 75 76 77 78 79 80 81 82 83 84 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 7 d 7 d 7 85 86 87 88 89 90 91 92 93 94 95 96 m d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7/8 d 7/8 97 98 99 100 101 102 103 104 105 106 107 108 d 7/8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 109 110 111 112 113 114 115 116 117 118 119 120 d 8 +++???+??+? pef 80902 functional description data sheet 17 2001-11-12 d 1 ... d 8 ternary 2b + d data of iom ? -2 frames 1 ... 8 m maintenance symbol +, ? syncword pef 80902 functional description data sheet 18 2001-11-12 u 1 ... u 8 ternary 2b + d data of iom ? -2 frames 1... 8 m maintenance symbol +, - syncword table 7 frame structure b for upstream transmission nt to lt 123456789101112 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 13 14 15 16 17 18 19 20 21 22 23 24 u 1/2 u 1/2 u 1/2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 25 26 27 28 29 30 31 32 33 34 35 36 m u 2 u 2 u 2 u 3 u 3 u 3 u 3 u 3 u 3 u 3 u 3 37 38 39 40 41 42 43 44 45 46 47 48 u 3 u 3 u 3 u 3 u 3/4 u 3/4 u 3/4 u 4 u 4 u 4 u 4 u 4 49 50 51 52 53 54 55 56 57 58 59 60 u 4 ?+??+???+++ 61 62 63 64 65 66 67 68 69 70 71 72 u 4 u 4 u 4 u 4 u 4 u 4 u 5 u 5 u 5 u 5 u 5 u 5 73 74 75 76 77 78 79 80 81 82 83 84 u 5 u 5 u 5 u 5 u 5 u 5 u 5/6 u 5/6 u 5/6 u 6 u 6 u 6 85 86 87 88 89 90 91 92 93 94 95 96 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 7 u 7 u 7 97 98 99 100 101 102 103 104 105 106 107 108 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7/8 u 7/8 u 7/8 109 110 111 112 113 114 115 116 117 118 119 120 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 pef 80902 functional description data sheet 19 2001-11-12 2.3.2 maintenance channel the 4b3t frame structure provides a 1 kbit/s m(aintenance)-channel for the transfer of remote loopback commands and error indications. loopback commands the lt station uses the m-channel to request remote loopbacks. loopback commands are coded with a series of ? 0 ? and ? + ? symbols. a continuous series of ? + ? requests for loopback 2 activation in the nt a continuous series of ? 0 ? requests for deactivation of any loopback the nt station reacts as soon as the pattern has been detected in 8 consecutive symbols. error indications the nt u-transceiver reports line code violations via the m-channel to the exchange by setting one m-bit to ? + ? polarity. transparent messages the exchange of transparent messages via the transparent channel is not supported by the t-sminto. 2.3.3 coding from binary to ternary data each 4 bit block of binary data is coded into 3 ternary symbols of mms 43 block code according to table 8 . the number of the next column to be used, is given at the right hand side of each block. the left hand signal elements in the table (both ternary and binary) are transmitted first. table 8 mms 43 coding table s1 s2 s3 s4 t t t t t 0 0010 ? +10 ? +20 ? +30 ? +4 0 111 ? 0+1 ? 0+2 ? 0+3 ? 0+4 0 100 ? +01 ? +02 ? +03 ? +04 0 010+ ? 01+ ? 02+ ? 03+ ? 04 1 011+0 ? 1+0 ? 2+0 ? 3+0 ? 4 1 1100+ ? 10+ ? 20+ ? 30+ ? 4 1 001+ ? +2+ ? +3+ ? +4 ??? 1 pef 80902 functional description data sheet 20 2001-11-12 2.3.4 decoding from ternary to binary data decoding is done in the reverse manner of coding. the received blocks of 3 ternary symbols are converted into blocks of 4 bits. the decoding algorithm is given in table 9 . as in the encoding table, the left hand symbol of each block (both binary and ternary) is the first bit and the right hand is the last. if a ternary block "0 0 0" is received, it is decoded to binary "0 0 0 0". this pattern usually occurs only during deactivation. 0 01100+200+300+4 ?? 02 1 1010+020+030+04 ? 0 ? 2 1 000+002+003+0040 ?? 2 0 110 ? ++2 ? ++3 ?? +2 ?? +3 1 010++ ? 2++ ? 3+ ?? 2+ ?? 3 1 111++0300 ? 100 ? 200 ? 3 0 000+0+30 ? 010 ? 020 ? 03 0 1010++3 ? 001 ? 002 ? 003 1 100+++4 ? + ? 1 ? + ? 2 ? + ? 3 table 9 4b3t decoding table ternary block binary block 0 0 0, + 0 +, 0 ? 0 0 0 0 0 0 ? + 0001 + ? 0 0 0 1 0 0 0 +, ? ? 0 0 0 1 1 ? + 0 0 1 0 0 0 + +, ? 0 0 0 1 0 1 ? + +, ? ? + 0 1 1 0 ? 0 + 0 1 1 1 + 0 0, 0 ? ? 1000 + ? +, ? ? ? 1001 + + ? ,+ ? ? 1010 + 0 ? 1011 + + +, ? + ? 1100 table 8 mms 43 coding table (cont ? d) s1 s2 s3 s4 pef 80902 functional description data sheet 21 2001-11-12 2.3.4.1 monitoring of code violations the running digital sum monitor (rdsm) computes the running digital sum from the received ternary symbols by adding the polarity of the received user data (+ 1, 0, ? 1). at the end of each block, the running digital sum is supposed to reflect the number of the next column in table 8 . a code violation has occurred if the running digital sum is less than one or more than four at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero polarity) is found in the received data. if at the end of a ternary block no error was found, the running digital sum retains its current value. if the counter value is greater than 4, it is set to 4 at the beginning of the next ternary block, if its value is 0 or less, it is set to one. so after a code violation has been detected, the rdsm synchronizes itself within a period depending on the received data pattern. note there are some transmission errors which do not cause a code violation. 2.3.5 scrambler / descrambler scrambler the binary transmit data from the iom ? -2 interface is scrambled with a polynomial of 23 bits, before it is sent to the 4b3t coder. the scrambler polynomial is:: descrambler the received data (after decoding from ternary to binary) is multiplied with a polynomial of 23 bits in order to recover the original data before it is forwarded to the iom ? -2 interface.the descrambler is self synchronized after 23 symbols. the descrambler polynomial is:: the scrambling / descrambling process is controlled fully by the t-sminto. hence, no influence can be taken by the user. 0 + 0, ? 0 ? 1101 0 + ? 1110 + + 0, 0 0 ? 1111 table 9 4b3t decoding table (cont ? d) z 23 ? z 18 ? 1 ++ z 23 ? z 5 ? 1 ++ pef 80902 functional description data sheet 22 2001-11-12 2.3.6 command/indication codes both commands and indications depend on the data direction. table 10 presents all defined c/i codes. a new command or indication will be recognized as valid after it has been detected in two successive iom ? -2 frames (double last-look criterion). indications are strictly state orientated. refer to the state diagrams in the following sections for commands and indications applicable in various states. table 10 c/i codes code in out 0000 tim dr 0001 ?? 0010 ?? 0011 ltd ? 0100 ? rsy 0101 ssp ? 0110 dt ? 0111 ?? 1000 ar ar 1001 reserved 1) 1) c/i code ? 1010 ? must not be input to the u-transceiver. ? 1010 ? arl 1011 ?? 1100 ai ai 1101 res ? 1110 ? ail 1111 di dc ai activation indication di deactivation indication. ail activation indication loop 2 dr deactivation request ar activation request ltd lt disable arl activation request local loop res reset dt data through mode rsy resynchronization indication pef 80902 functional description data sheet 23 2001-11-12 2.3.7 state machine for activation and deactivation 2.3.7.1 state machine notation the following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. the states with its inputs and outputs are interpreted as shown below: figure 5 state diagram example each state has one or more transitions to other states. these transitions depend on certain conditions which are noted next to the transition lines. these conditions are the only possibility to leave a state. if more conditions have to be fulfilled together, they are put into parentheses with an and operator (&). if more than one condition leads to the same transition, they are put into parentheses with an or operator (|). the meaning of a condition may be inverted by the not operator (/). only the described states and transitions exist. at some transitions, an internal timer is started. the start of a timer is indicated by txs ( ? x ? is the timer number). transitions that are caused if a timer has expired are labelled by txe. some conditions lead to the same target state. to reduce the number of lines and the complexity of the figures, a state named ? any state ? acts on behalf of all state. dc deactivation confirmation ssp send-single-pulses tim timing request c/i channel indication (dout) out state name transmitted u-signal sm_expl.emf pef 80902 functional description data sheet 24 2001-11-12 the state machines are designed to cope with all isdn devices with iom ? -2 standard interfaces. undefined situations are excluded. in any case, the involved devices will enter defined conditions as soon as the line is deactivated. 2.3.7.2 awake protocol for the awake process two signals are defined ? u1w ? and ? u2w ? . depending on the call direction (up-, downstream) u1w and u2w are interpreted as awake or acknowledge signals (see figures below). figure 6 awake procedure initiated by the lt figure 7 awake procedure initiated by the nt 2.133 ms info u2w lt info u2 (a) 2.133 ms info u1w nt info u1a 12 ms 7 ms 13 ms itd06385.vsd 2. 133 ms info u1w nt 13 ms info u1a 6 ms 2. 133 ms info u2w lt info u2 (a) 7 ms itd06386.vsd pef 80902 functional description data sheet 25 2001-11-12 acting as calling station after sending the awake signal, the awaking u-transceiver waits for the acknowledge. after 12 ms, the awake signal is repeated, if no acknowledge has been recognized. if an acknowledge signal has been recognized, the u-transceiver waits for its possible repetition (in case of previous coincidence of two awake signals). if no repetition was detected, the u-transceiver starts transmitting u2 with a delay of 7 ms. if such a repetition is detected, the u-transceiver interprets it as an awake signal and behaves like a device awoken by the far end. acknowledging a wake-up call if a deactivated device detects an awake signal on u, an acknowledge signal is sent out. after that, the u-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn ? t been recognized). if no repetition is found, the awoken u-transceiver starts sending u2 after 7 ms from detecting the awake signal. if a repeated awake signal is found, the procedure in the awoken u-transceiver starts again. pef 80902 functional description data sheet 26 2001-11-12 2.3.7.3 nt state machine (iec-t / ntc-t compatible) figure 8 nt state machine (iec-t/ntc-t compatible) note: the test modes ?data through? (dt), ?send single pulses? (ssp) and ?quiet mode? (qm) can be generated via pins tm0-2 according to table 5 . awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp or ltd (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 (u0 & t12e) u2 t12s t13e ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai / ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0 synchronizing rsy u1a pef 80902 functional description data sheet 27 2001-11-12 2.3.7.4 inputs to the u-transceiver c/i-commands ai activation indication the downstream device issues this indication to announce that layer 1 is available. the u-transceiver in turn informs the lt side by transmitting u3. ar activation request the u-transceiver is requested to start the activation process (if not already done) by sending the wake-up signal u1w. di deactivation indication this indication is used during a deactivation procedure to inform the u- transceiver that it may enter the ? deactivated ? (power-down) state. dt data through test mode this unconditional command is used for test purposes only and forces the u- transceiver into state ? transparent ? . table 11 differences to the former nt-sm of the iec-t/ntc-t no. state/ signal change comment 1. state ? deact. request rec. ? split into 3 states - ? pend. deactivation 1 ? - ? reset ? state - ? test ? state simplifies sm implementation 2. state ? loss of framing ? new inserted, results in different behavior in state ? transparent ? , no return to normal transmission possible after detection of lof compliance to etsi ts 102 080, corresponds to state nt1.10 3. c/i-code ltd new inserted 4. state ? power down ? renamed to state ? deactivated ? for consistency reasons to 2b1q 5. state ? data transmission ? renamed to state ? transparent ? 6. timer variables introduced name duration see table 12 pef 80902 functional description data sheet 28 2001-11-12 ltd lt disable this unconditional command forces the u-transceiver to state ? test ? , where it transmits u0. no further action is initiated. res reset unconditional command which resets the u-transceiver. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. tim timing the u-transceiver is requested to enter state ? iom awaked ? . u-interface events u0 u0 detected u0 is recognized after 120 symbols (1ms) with zero level in a row. detection may last up to 2 ms. u2 u2 detected the u-transceiver detects u2 if continuous binary 0 ? s are found after descrambling and lof = 0 for at least 8 subsequent u-frames. u2 is detected after 8 to 9 ms. u4h u4h detected u4h is recognized, if the u-transceiver detects 16 subsequent binary 1 ? s after descrambling. awr awake signal (u2w) detected awt awake signal (u1w) has been sent out lof loss of framing on u-interface txe timer ended, the started timer has expired timers the start of timers is indicated by txs, the expiry by txe. the following table shows which timers are used. table 12 timers timer duration (ms) function state t05 0.5 c/i code recognition pend. deactivation, deactivating t6 6 supervises u1w repetition start awaking uk0 pef 80902 functional description data sheet 29 2001-11-12 2.3.7.5 outputs of the u-transceiver below the signals and indications are summarized that are issued on iom ? -2 (c/i indications) and on the u-interface (predefined u-signals). c/i indications ai activation indication the u-transceiver has established transparency of transmission. the downstream device is requested to establish layer-1 functionality. ail activation indication loop-back the u-transceiver has established transparency of transmission. the downstream device is requested to establish a loopback #2. ar activation request the downstream device is requested to start the activation procedure. arl activation request loop-back the u-transceiver has detected a loop-back 2 command in the m-channel and has established transparency of transmission in the direction iom ? to u- interface. the downstream device is requested to start the activation procedure and to establish a loopback #2. dc deactivation confirmation idle code on the iom ? -2 interface. dr deactivation request the u-transceiver has detected a deactivation request command from the lt- side for a complete deactivation. the downstream device is requested to start the deactivation procedure. rsy resynchronizing indication rsy informs the downstream device that the u-transceiver is not synchronous. t12 12 prevents the u-transceiver in state synchronizing from immediate transition to state ? pend. deactivation ? if u0 is detected synchronizing t13 13 supervises u2w repetition ack. sent / received sending awake-ack. table 12 timers (cont ? d) timer duration (ms) function state pef 80902 functional description data sheet 30 2001-11-12 signals on u-interface the signals u0, u1w, u1a, u1, u3, u5 and sp are transmitted on the u-interface.they are defined in table 17 . signals on iom ? -2 the data (b+b+d) is set to all ? 1 ? s in all states besides the states listed in table 13 . dependence of outputs the m-symbol output in states with valid m-symbol output its value is set according to table 14 : 2.3.7.6 nt-states in this section each state is described with its function. table 13 active states sbc sychronizing wait for info u4h transparent table 14 m symbol output rds error not detected detected m symbol output ? 0 ? ? + ? table 15 signal output on uk0 in state test input ssp active all other except c/i-code ? di ? signal output on uk0 sp u0 table 16 c/i-code output loopback command sbc synchronizing wait for info u4h transparent not received ar ar ai received arl arl ail pef 80902 functional description data sheet 31 2001-11-12 acknowledge sent / receive after having sent the awake signal, the u-transceiver has received the acknowledge wake tone. if being awoken the u-transceiver has sent the acknowledge. in both cases the u-transceiver waits for possible repetition or time-out. awake signal sent the nt has sent out the awake signal u1w and waits now for a response. if the lt does not react in time timer t6 expires and the nt repeats its wake-up call. deactivated only in ? deactivated ? state the device may enter the power-down mode. deactivating state deactivating assures that the c/i-channel code dc is issued four times before entering the ? deactivated ? state. iom ? awaked the u-transceiver is deactivated, but may not enter the power-down mode. loss of framing this state is entered on loss of framing (lof). no signal is transmitted on the u-interface. a receiver-reset is performed by. note that there is no return to the ? transparent ? state that has been possible before in the former iec-t based state machine. pending deactivation the u-transceiver has received u0. the u-transceiver remains at least 0.5ms in this state before it accepts di. sbc synchronizing the nt is now synchronized and indicates this by ar/arl towards the downstream device. the nt waits for the acknowledge ? ai ? from the downstream device. sending awake-ack. on the receipt of the awake signal u2w the u-transceiver responds with the transmission of u1w. pef 80902 functional description data sheet 32 2001-11-12 start awaking uk0 on the receipt of ar in the c/i-channel the u-transceiver sends the awake signal u1w to start an activation. synchronizing after the successful awake procedure the u-transceiver trains its receiver coefficients until it is able to detect the signals u2. reset in state ? reset ? a software-reset is performed. test state ? test ? is entered when the unconditional commands tm2-0= ? ssp ? is applied. the test signal ssp is issued as long as pin ssp is active or c/i=ssp is applied. transparent the transmission line is fully activated. user data is transparently exchanged by u4/u5. transparent state is entered in the case of a loopback 2. the downstream device is informed by c/i code ai that the transparent state has been reached note that in contrast to the former iec-t state machine there is no resynchronization mechanism. once loss of framing (lof) has been detected a deactivation is initiated. wait for info u4h the nt is synchronized and waits now for the permission (u4h) to go to the ? transparent ? state. pef 80902 functional description data sheet 33 2001-11-12 2.4 s-transceiver the s-transceiver offers the nt state machine described in the user ? s manual v3.4 [8]. the s-transceiver basic configurations are performed via pin strapping. 2.4.1 line coding, frame structure line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. figure 9 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 9 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. 011 code violation pef 80902 functional description data sheet 34 2001-11-12 figure 10 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. 2.4.2 s/q channels, multiframing the s/q channels are not supported. ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multi-frame f a pef 80902 functional description data sheet 35 2001-11-12 2.4.3 data transfer between iom -2 and s 0 in the state g3 (activated) the b1, b2 and d bits are transferred transparently from the s/t to the iom -2 interface and vice versa. in all other states ? 1 ? s are transmitted to the iom -2 interface. 2.4.4 loopback 2 c/i commands arl and ail close the analog loop as close to the s-interface as possible. etsi refers to this loop under ? loopback 2 ? . etsi requires, that b1, b2 and d channels have the same propagation delay when being looped back. the d-channel echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). the loop is transparent. note: after c/i-code ail has been recognized by the s-transceiver, zeros are looped back in the b and d-channels (du) for four frames. 2.4.5 state machine the state diagram notation is given in figure 11 . the information contained in the state diagrams are: ? state name ? signal received from the line interface (info) ? signal transmitted to the line interface (info) ? c/i code received (commands) ? c/i code transmitted (indications) ? transition criteria the transition criteria are grouped into: ? c/i commands ? signals received from the line interface (infos) ? reset pef 80902 functional description data sheet 36 2001-11-12 figure 11 state diagram notation as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? ? stands for a logical and combination. and a ? + ? indicates a logical or combination. test signals 2 khz single pulses (tm1) one pulse with a width of one bit period per frame with alternating polarity. 96 khz continuous pulses (tm2) continuous pulses with a pulse width of one bit period. note: the test signals tm1 and tm2 can be generated via pins tm0-2 according to table 5 . reset states after an active signal on the reset pin rst the s-transceiver state machine is in the reset state. c/i codes in reset state in the reset state the c/i code 0000 (tim) is issued. this state is entered after a hardware reset (rst ). c/i codes in deactivated state if the s-transceiver is in state ? deactivated ? and receives i0 , the c/i code 0000 (tim) is issued until expiration of the 8 ms timer. otherwise, the c/i code 1111 (di) is issued. receive infos on s/t i0 info 0 detected iom-2 interface c/i code macro_17.vsd state ind. cmd. i x i r s/t interface info in out unconditional transition pef 80902 functional description data sheet 37 2001-11-12 i0 level detected (signal different to i0) i3 info 3 detected i3 any info other than info 3 transmit infos on s/t i0 info 0 i2 info 2 i4 info 4 it send single pulses (tm1). send continuous pulses (tm2). pef 80902 functional description data sheet 38 2001-11-12 2.4.5.1 state machine nt mode figure 12 state machine nt mode note: by setting the test mode pins tm0-2 to ?010? / ?011?: continuous pulses / single pulses, the s-transceiver starts sending the corresponding test signal, but no state transition is invoked. g2 pend. act ar ard i2 i3 reset tim res i0 * g1 i0 detected ar dc i0 * g2 lost framing s/t rsy aid ard i2 i3 g1 deactivated di tim dc i0 i0 statem_nt_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 i3*aid 2) rst ard 1) g2 wait for aid ai ard i2 i3 g3 lost framing u rsy rsy i2 * g3 activated ai aid i4 i3 ard 1) aid 2) i3*ard 1) i3*ard dr dr dr rsy rsy dr rsy ard 1) aid 2) 1) : ard = ar or arl 2) : aid =ai or ail ard 1) i3*aid 2) (i0*8ms) pef 80902 functional description data sheet 39 2001-11-12 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom -2 interface. g1 i0 detected an info 0 is detected on the s/t-interface, translated to an ? activation request ? indication in the c/i channel. the s-transceiver is waiting for an ar command, which normally indicates that the transmission line upstream is synchronized. g2 pending activation as a result of the ard command, an info 2 is sent on the s/t-interface. info 3 is not yet received. in case of arl command, loop 2 is closed. g2 wait for aid info 3 was received, info 2 continues to be transmitted while the s-transceiver waits for a ? switch-through ? command aid from the device upstream. g3 activated info 4 is sent on the s/t-interface as a result of the ? switch through ? command aid: the b and d-channels are transparent. on the command ail, loop 2 is closed. g2 lost framing s/t this state is reached when the transceiver has lost synchronism in the state g3 activated. g3 lost framing u on receiving an rsy command which usually indicates that synchronization has been lost on the transmission line, the s-transceiver transmits info 2. g4 pending deactivation this state is triggered by a deactivation request dr, and is an unstable state. indication di (state ? g4 wait for dr ? ) is issued by the transceiver when: either info0 is received for a duration of 16 ms or an internal timer of 32 ms expires. pef 80902 functional description data sheet 40 2001-11-12 g4 wait for dr final state after a deactivation request. the s-transceiver remains in this state until dc is issued. unconditional states test mode tm1 send single pulses test mode tm2 send continuous pulses c/i commands command abbr. code remark deactivation request dr 0000 deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. activation indication ai 1100 activation indication. synchronous receiver, i.e. activation completed. pef 80902 functional description data sheet 41 2001-11-12 activation indication loop ail 1110 activation indication loop deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during deactivation procedure. receiver not synchronous rsy 0100 receiver is not synchronous. activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request. command abbr. code remark pef 80902 operational description data sheet 42 2001-11-12 3 operational description 3.1 layer 1 activation/deactivation 3.1.1 generation of 4b3t signal elements for control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by ts 102 080 and ftz 1 tr 220. table 17 4b3t signal elements u0 no signal or deactivation signal that is used in both directions. downstream, it requests the nt to deactivate. upstream, the nt acknowledges by u0 that it is deactivated. u1w, u2w awake or awake acknowledge signal used in the awake procedure of the u-interface. u2 the lt sends u2 to enable the own echo canceller to adapt the coefficients. by the barker code the nt at the other end is enabled to synchronize. the detection of u2 is used by the nt as a criterion for synchronization. the m-channel on u may be used to transfer loop commands. u2a while the nt-rp is synchronizing on the received signal, the lt-rp sends out u2a to enable its echo canceller to adapt the coefficients, but sending no barker code it inhibits the nt to synchronize on the still asynchronous signal. due to proceeding synchronization, the u-frame may jump from time to time. u2a can not be detected in the nt at the far end. u1a u1a is similar to u1 but without framing information. while the nt synchronizes on the received signal, it sends out u1a to enable its echo canceller to adapt its coefficients, but sends no barker code to prevent the lt from synchronizing on the still asynchronous signal. due to proceeding synchronization, the u-frame may jump from time to time. u1a can not be detected by the far-end lt. u1 when synchronized, the nt sends the barker code and the lt may synchronize itself. u1 indicates additionally that a terminal equipment has not yet activated. upon receiving u1 the lt indicates the synchronized state by c/i ? uai ? to layer-2. usually during activation, no u1 signal is detected in the lt because the te is activated first and u1 changes to u3 before being detected. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. pef 80902 operational description data sheet 43 2001-11-12 u3 u3 indicates that the whole link to the te is synchronous in both directions. on detecting u3 the lt requests the nt by u4h to establish a fully transparent connection. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. u4h u4h requires the nt to go to the ? transparent ? state. on detecting u4h the nt stops sending signal u3 and informs the s-transceiver or a layer-2 device via the system interface. the m-channel on u may be used to transfer loop commands and 1 kbit/s transparent data. u4 u4 transports operational data on b and d channels. the m-channel on u may be used to transfer loop commands and 1 kbit/s transparent data. u5 u5 transports operational data on b and d channels. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. sp the t-sminto sends periodically single pulses once per millisecond on the u-interface. the test mode can be used for pulse mask measurements. lof loss of frame, generated by flywheel table 18 generation of the 4b3t signal elements upstream (nt to lt) downstream (lt to nt) symbols (ternary) sync word (tern ary) m sym bol (tern ary) binary data before scram bling u1w u2w resulting in a tone of: frequency: 7.5 khz duration: 2.13 ms when sending the wakeup tone is finished, signal awt is set and ternary "0" is sent 16 times + + + + + + + + ? ? ? ? ? ? ? ? n/a n/a n/a u1a u2a scrambled binary data 0 0 0 u1 u2 scrambled binary data yes yes 0 u3 scrambled binary data yes yes 1 table 17 4b3t signal elements (cont ? d) pef 80902 operational description data sheet 44 2001-11-12 table 19 s/t-interface signals u4h duration: 1 ms (warranted by state machine) yes yes 1 u5 u4 binary data from the digital interface yes yes bbd u0 u0 ternary continuous "0" 0 0 0 n/a sp sp single pulses once "+", 119 times "0" (repeatedl y) n/a n/a n/a signals from nt to te signals from te to nt info 0 no signal. info 0 no signal. info 1 a continuous signal with the following pattern: positive zero, negative zero, six ones. info 2 frame with all bits of b, d, and d-echo channels set to binary zero. bit a set to binary zero. n and l bits set according to the normal coding rules. info 3 synchronized frames with operational data on b and d-channels. info 4 frames with operational data on b, d, and d-echo channels. bit a set to binary one. table 18 generation of the 4b3t signal elements (cont ? d) pef 80902 operational description data sheet 45 2001-11-12 3.1.2 complete activation initiated by exchange figure 13 activation initiated by exchange note: the lt starts issuing signal u2 before the nt starts issuing u1a. this chronological order is not displayed for clarification. iom -2 te s/t-reference point nt u-reference point lt iom -2 dc info 0 dc u0 di info 0 di di actbylt_tsmint.vsd u0 u0 rsy ar ar u0 ar dc u1w u1a u2 u1 u2w ar info 2 ai u3 info 3 ar u4h u5 uai ai info 4 ai ar8/10 s 0 u k0 dfe-t sbcx-x or ipac-x u4 ai 1 ms uai pef 80902 operational description data sheet 46 2001-11-12 3.1.3 complete activation initiated by te figure 14 activation initiated by te note: the lt starts issuing signal u2 before the nt starts issuing u1a. this chronological order is not displayed for clarification. iom -2 te s/t-reference point nt u-reference point lt iom -2 dc info 0 dc u0 dc di info 0 di u0 di tim pu ar8/10 info 1 tim ar ar info 2 rsy info 0 info 3 ar ai ai info 4 ai u1w u0 u2w u0 u1a u2 actbyte_tsmint.vs d ar sbcx-x or ipac-x s 0 u k0 dfe-t rsy u1 u3 u4h u5 uai u4 ai 1 ms 8ms uai pef 80902 operational description data sheet 47 2001-11-12 3.1.4 deactivation figure 15 deactivation (always initiated by lt) iom -2 te s/t-reference point nt u-reference point lt iom -2 ai info 4 ai u4 ar ar info 3 ai ai tim deac_tsmint.vsd dc u5 dr deac u0 u0 dr info 0 dc di dc di sbcx-x or ipac-x s 0 u k0 dfe-t info 0 di dr rsy pef 80902 operational description data sheet 48 2001-11-12 3.1.5 activation procedures with loopback #2 figure 16 activation of loopback #2 note: closing/resolving loop 2 may provoke the s-transceiver to resynchronize. in this case, the following c/i-codes are exchanged immediately on reception of ail/ai, respectively: du: ?rsy?, du: ?ai?, dd: ?ail?/?ai?. iom -2 te s/t-reference point nt u-reference point lt iom -2 ai info 4 u4 ar8/10 info 3 ai act_loop2_tsmint.vsd u5 ar ai ai 2b+d 2b+d 2b+d ail lp2i = 0 u4 (m-bit= 8x '+' ) ar2 ai u4 (m-bit= 8x '0' ) ar lp2i = 1 sbcx-x or ipac-x s 0 u k0 dfe-t pef 80902 operational description data sheet 49 2001-11-12 3.2 layer 1 loopbacks test loopbacks are specified by the national ptts in order to facilitate the location of defect systems. four different loopbacks are defined. the position of each loopback is illustrated in figure 17 . figure 17 test loopbacks loopbacks #1, #1a and #2 are controlled by the exchange. loopback #3 is controlled locally on the remote side. all four loopback types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. only the data looped back internally is processed; signals on the receive pins are ignored. the propagation delay of actually looped b and d channels data must be identical in all loopbacks. 3.2.1 loopback no.2 the following loopback type belongs to the loopback-#2 category: complete loopback (b1,b2,d), in a downstream device normally loopback #2 is controlled by the exchange. the maintenance channel is used for this purpose. 3.2.1.1 complete loopback when receiving the request for a complete loopback, the u transceiver passes it on to the s-bus transceiver. this is achieved by issuing the c/i-code ail in the ? transparent ? state or c/i = arl in states different than ? transparent ? iom ? -2 pbx or te u-transceiver iom ? -2 iom ? -2 iom ? -2 u-transceiver u-transceiver u-transceiver u-transceiver u-transceiver loop 2 loop 3 loop 2 loop 1 a loop 2 loop 1 s-bus nt u u loop 2 repeater (optional) s-transceiver layer-1 controller layer-1 controller iom-2 exchange loop_2b1q.emf pef 80902 operational description data sheet 50 2001-11-12 3.3 external circuitry 3.3.1 power supply blocking recommendation the following blocking circuitry is suggested. figure 18 power supply blocking 3.3.2 u-transceiver the t-sminto is connected to the twisted pair via a transformer. figure 19 shows the recommended external circuitry with external hybrid. the recommended protection circuitry is not displayed. vddd vddd vssd vssd vdda_sr vdda_ur vdda_ux vdda_sx vssa_ur vssa_ux vssa_sr vssa_sx 100nf 100nf 100nf 100nf 100nf 100nf gnd 3.3v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) blocking_caps_smint.vsd pef 80902 operational description data sheet 51 2001-11-12 figure 19 external circuitry u-transceiver with external hybrid u-transformer parameters the following table lists parameters of typical u-transformers. table 20 u-transformer parameters u-transformer parameters symbol value unit u-transformer ratio; device side : line side n1 : 1.6 main inductanc of windings on the line side l h 7.5 mh leakage inductance of windings on the line side l s 120 h coupling capacitance between the windings on the device side and the windings on the line side c k 30 pf dc resistance of the windings on device side r b 0.9 ? dc resistance of the windings on line side r l 1.8 ? loop aout bout ain bin n c r t r4 r comp r comp >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 80902 operational description data sheet 52 2001-11-12 resistors of the external hybrid r3, r4 and r t r3 = 1.75 k ? r4 = 1.0 k ? r t = 25 ? resistors r comp / r t optional use of trafos with non negligible resistance r b , r l requires compensation resistors r comp depending on r b and r l : n 2 (2r comp + r b ) + r l = 20 ? (1) compliance with return loss measurements: n 2 (2r comp + 2r t + r out + r b ) + r l = 150 ? (2) r b , r l : see table 20 r out : see table 25 15nf capacitor to achieve optimum performance the 15nf capacitor should be mkt. a ceramic capacitor is not recommended. tolerances rs: 1% c = 15nf: 10-20% l h = 7.5mh: 10% 3.3.3 s-transceiver in order to comply to the physical requirements of itu recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the s-transceiver needs some additional circuitry. pef 80902 operational description data sheet 53 2001-11-12 s-transformer parameters the following table 21 lists parameters of a typical s-transformer: table 21 s-transformer parameters transmitter the transmitter requires external resistors r stx = 47 ? in order to adjust the output voltage to the pulse mask (nominal 750 mv according to itu i.430, to be tested with the test mode ? tm1 ? ) on the one hand and in order to meet the output impedance of minimum 20 ? on the other hand (to be tested with the testmode ? continuous pulses ? ) on the other hand. note: the resistance of the s-transformer must be taken into account when dimensioning the external resistors r stx . if the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. transformer parameters symbol value unit transformer ratio; device side : line side n 2 : 1 main inductance of windings on the line side l h typ. 30 mh leakage inductance of windings on the line side l s typ. <3 h coupling capacitance between the windings on the device side and the windings on the line side c k typ. <100 pf dc resistance of the windings on device side r b typ. 2.4 ? dc resistance of the windings on line side r l typ. 1.4 ? pef 80902 operational description data sheet 54 2001-11-12 figure 20 external circuitry s-interface transmitter receiver the receiver of the s-transceiver is symmetrical. 10 k ? overall resistance are recommended in each receive path. it is preferable to split the resistance into two resistors for each line. this allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 khz input impedance test of itu i.430 [6] and ets 300012-1). the remaining resistance (1.8 k ? ) protects the s- transceiver itself from input current peaks. figure 21 external circuitry s-interface receiver 20...40 47 sx1 sx2 2 : 1 gnd v dd 47 dc point extcirc_s.vsd 1k8 1k8 sr1 sr2 2 : 1 gnd v dd 8k2 8k2 dc point extcirc_s.vsd pef 80902 operational description data sheet 55 2001-11-12 3.3.4 oscillator circuitry figure 22 illustrates the recommended oscillator circuit. figure 22 crystal oscillator table 22 crystal parameters external components and parasitics the load capacitance c l is computed from the external capacitances c ld , the parasitic capacitances c par (pin and pcb capacitances to ground and v dd ) and the stray capacitance c io between xin and xout: for a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances c ld , which is usually the only variable to be determined by the circuit designer. typical values for the capacitances c ld connected to the crystal are 22 - 33 pf. 3.3.5 general ? low power leds parameter symbol limit values unit frequency f 15.36 mhz frequency calibration tolerance +/-60 ppm load capacitance c l 20 pf max. resonance resistance r1 20 ? max. shunt capacitance c 0 7pf oscillator mode fundamental 15.36 mhz xout xin c ld c ld c l c ld c par + () c ld c par + () c ld c par + () c ld c par + () + ------------------------------------------------------------------------ c io + = pef 80902 electrical characteristics data sheet 56 2001-11-12 4 electrical characteristics 4.1 absolute maximum ratings esd integrity (according eia/jesd22-a114b (hbm)): 2 kv note: stress above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. line overload protection the t-smint o is compliant to esd tests according to ansi / eos / esd-s 5.1-1993 (cdm), eia/jesd22-a114b (hbm) and to latch-up tests according to jedec eia / jesd78. from these tests the following max. input currents are derived ( table 23 ): parameter symbol limit values unit ambient temperature under bias t a -40 to 85 c storage temperature t stg ? 65 to 150 c maximum voltage on v dd v dd 4.2 v maximum voltage on any pin with respect to ground v s -0.3 to v dd + 3.3 (max. < 5.5) v table 23 maximum input currents test pulse width current remarks esd 100 ns 1.3 a 3 repetitions latch-up 5 ms +/-200 ma 2 repetitions, respectively dc -- 10 ma pef 80902 electrical characteristics data sheet 57 2001-11-12 4.2 dc characteristics table 24 s-transceiver characteristics v dd / v dda = 3.3 v +/- 5% ; v ss / v ssa = 0 v; t a = -40 to 85 c digital pins parameter symbol limit values unit test condition min. max. all input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 5.25 v all except dd/du act ,lp2i mclk output low voltage v ol1 0.45 v i ol1 = 3.0 ma output high voltage v oh1 2.4 v i oh1 = 3.0 ma dd/du act ,lp2i mclk output low voltage v ol2 0.45 v i ol2 = 4.0 ma output high voltage (dd/du push-pull) v oh2 2.4 v i oh2 = 4.0 ma all input leakage current i li 10 a 0 v v in v dd output leakage current i lo 10 a 0 v v in v dd input leakage current (internal pull-up) i lipu 50 200 a 0 v v in v dd analog pins ain, bin input leakage current i li 30 a 0 v v in v d d pin parameter symbol limit values unit test condition min. typ. max. sx1,2 absolute value of output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.2 2.31 v r l = 50 ? sx1,2 s-transmitter output impedance z x 10 34 k ? see 1) 0 see 2)3) sr1,2 s-receiver input impedance z r 10 100 k ? ? v dd = 3.3 v v dd = 0 v pef 80902 electrical characteristics data sheet 58 2001-11-12 table 25 u-transceiver characteristics 1) requirement itu-t i.430, chapter 8.5.1.1a): ? at all times except when transmitting a binary zero, the output impedance , in the frequency range of 2khz to 1 mhz, shall exceed the impedance indicated by the template in figure 11. the requirement is applicable with an applied sinusoidal voltage of 100 mv (r.m.s value) ? 2) requirement itu-t i.430, chapter 8.5.1.1b): ? when transmitting a binary zero, the output impedance shall be > 20 ? . ? : must be met by external circuitry. 3) requirement itu-t i.430, chapter 8.5.1.1b), note: ? the output impedance limit shall apply for a nominal load impedance (resistive) of 50 ? . the output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. the peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. the limitation applies for pulses of both polarities. ? limit values unit min. typ. max. receive path signal / (noise + total harmonic distortion) 1) 1) test conditions: 1.4 vpp differential sine wave as input on ain/bin with long range (low, critical range). 65 2) 2) versions pef 8x913 with enhanced performance of the u-interface are tested with tightened limit values db dc-level at ad-output 45 50 55 % 3) 3) the percentage of the "1 "-values in the pdm-signal. threshold of level detect (measured between ain and bin with respect to zero signal) 10 23 mv peak input impedance ain/bin 80 k ? transmit path signal / (noise + total harmonic distortion) 4) 4) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 70 db below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. 70 db common mode dc-level 1.61 1.65 1.69 v offset between aout and bout 35 mv absolute peak voltage for a single +3 or -3 pulse measured between aout and bout 5) 5) the signal amplitude measured over a period of 1 min. varies less than 1%. 2.42 2.5 2.58 v output impedance aout/bout: power-up power-down 0.8 3 1.5 6 ? ? pef 80902 electrical characteristics data sheet 59 2001-11-12 4.3 capacitances t a = 25 c, 3.3 v 5 % v ssa = 0 v, v ssd = 0 v, f c = 1 mhz, unmeasured pins grounded. 4.4 power consumption 4.5 supply voltages vdd d = + vdd 5% vdd a = + vdd 5% the maximum sinusoidal ripple on vdd is specified in the following figure: table 26 pin capacitances parameter symbol limit values unit remarks min. max. digital pads: input capacitance i/o capacitance c in c i/o 7 7 pf pf analog pads: load capacitance c l 3 pf pin ain, bin power consumption vdd=3.3 v, vss=0 v, inputs at vss/vdd, no led connected, 50% bin. zeros, no output loads except sx1,2 (50 ? 1) ) 1) 50 ? (2 x tr) on the s-bus. parameter limit values unit test condition min. typ. max. operational u and s enabled, iom -2 off 185 165 mw mw u: etsi loop 1 (0 m) u: etsi loop 2 (typical line) power down 15 mw pef 80902 electrical characteristics data sheet 60 2001-11-12 figure 23 maximum sinusoidal ripple on supply voltage 80 100 frequency / khz 10 100 mv (peak) 200 supply voltage ripple frequency ripple itd04269.vsd 60 pef 80902 electrical characteristics data sheet 61 2001-11-12 4.6 ac characteristics t a = -40 to 85 c, v dd = 3.3 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 24 . figure 24 input/output waveform for ac tests parameter all output pins symbol limit values unit min max fall time 30 ns rise time 30 ns device under test c load =50 pf 2.4 0.45 2.0 0.8 0.8 2.0 test points its00621.vsd pef 80902 electrical characteristics data sheet 62 2001-11-12 4.6.1 iom-2 interface figure 25 iom ? -2 interface - bit synchronization timing figure 26 iom-2 interface - frame synchronization timing note: at the start and end of a reset period, a frame jump may occur. this results in a dcl and fsc high time of min. 130 ns after this specific event. t 7 dcl last bit first bit du/dd (output) t 6 t 8 bit n bit n+1 du/dd (output) fsc dcl t 9 t 10 t 2 t 3 t 1 pef 80902 electrical characteristics data sheet 63 2001-11-12 parameter iom ? -2 interface symbol limit values unit min typ max dcl period t 1 1875 1953 2035 ns dcl high t 2 850 960 1105 ns dcl low t 3 850 960 1105 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 100 ns output data from active to high impedance t 7 100 ns output data delay from clock t 8 80 ns fsc high t 9 50% of fsc cycle time ns fsc advance to dcl t 10 65 130 195 ns dcl, fsc rise/fall t 15 30 ns data out rise/fall (c l = 50 pf, tristate) t 17 150 ns pef 80902 electrical characteristics data sheet 64 2001-11-12 4.6.2 reset table 27 reset input signal characteristics figure 27 reset input signal parameter symbol limit values unit test conditions min. typ. max. length of active low state t rst 4 ms power on the 4 ms are assumed to be long enough for the oscillator to run correctly 2 x dcl clock cycles + 400 ns after power on t rst rst itd09823.vsd pef 80902 electrical characteristics data sheet 65 2001-11-12 4.6.3 undervoltage detection characteristics figure 28 undervoltage control timing table 28 parameters of the uvd/por circuit v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. detection threshold 1) v det 2.7 2.8 2.92 v v dd = 3.3 v 5 % hysteresis v hys 30 90 mv max. rising/falling v dd edge for activation/ deactivation of uvd dv dd /dt 0.1 v/s max. rising v dd for power-on 2) 0.1 v/ ms min. operating voltage v ddmin 1.5 v v dd v ddmin v det t t rsto t act t act t deact t deact v hys vdddet.vsd pef 80902 electrical characteristics data sheet 66 2001-11-12 delay for activation of rsto t act 10 s delay for deactivation of rsto t deact 64 ms 1) the detection threshold v det is far below the specified supply voltage range of analog and digital parts of the t-smint ? . therefore, the board designer must take into account that a range of voltages is existing, where neither performance and functionality of the t-smint ? are guaranteed, nor a reset is generated. 2) if the integrated power-on reset of the t-sminto is selected (vdddet = ? 0 ? ) and the supply voltage v dd is ramped up from 0v to 3.3v +/- 5%, then the t-sminto is kept in reset during v ddmin < v dd < v det + v hys . v dd must be ramped up so slowly that the t-sminto leaves the reset state after the oscillator circuit has already finished start-up. the start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. pef 80902 package outlines data sheet 67 2001-11-12 5 package outlines plastic package, p-mqfp-44 (metric quad flat package) pef 80902 appendix: differences between q- and t-smint?o data sheet 68 2001-11-12 6 appendix: differences between q- and t-smint o the q- and t-smint o have been designed to be as compatible as possible. however, some differences between them are unavoidable due to the different line codes 2b1q and 4b3t used for data transmission on the u k0 line. especially the pin compatibility between q- and t-smint o allows for one single pcb design for both series with only some mounting differences. the following chapter summarizes the main differences between the q- and t- smint o. 6.1 pinning 6.1.1 pin definitions and functions 6.1.2 led pin act the 4 led states (off, fast flashing, slow flashing, on), which can be displayed with pin act , are slightly different for q- and t-smint o (see table 30 ). table 29 pin definitions and functions pin mqfp-44 q-smint o: 2b1q t-smint o: 4b3t 10 triple-last-look (tll ) tie to ? 1 ? 11 metallic termination input (mti) tie to ? 1 ? 16 auto u activation (aua) tie to ? 1 ? 17 cold start only (cso) tie to ? 1 ? 38 power status (primary) (ps1) tie to ? 1 ? 26 power status (secondary) (ps2) tie to ? 1 ? table 30 act states led states pin act q-smint o: 2b1q t-smint o: 4b3t off v dd v dd fast flashing 8hz (1 : 1)* 2hz (1 : 1)* pef 80902 appendix: differences between q- and t-smint?o data sheet 69 2001-11-12 note: * denotes the duty cycle ?high? : ?low?. 6.2 u-transceiver 6.2.1 u-interface conformity slow flashing 1hz (1 : 1)* 1hz (3 : 1)* on gnd gnd table 31 related documents to the u-interface q-smint o: 2b1q t-smint o: 4b3t etsi: ts 102 080 conform to annex a compliant to 10 ms interruptions conform to annex b ansi: t1.601-1998 (revision of ansi t1.601- 1992) conform mlt input and decode logic not required cnet: st/laa/elr/dnp/ 822 conform not required rc7355e conform not required ftz-richtlinie 1 tr 220 not required conform table 30 act states (cont ? d) led states pin act q-smint o: 2b1q t-smint o: 4b3t pef 80902 appendix: differences between q- and t-smint?o data sheet 70 2001-11-12 6.2.2 u-transceiver state machines figure 29 ntc-q compatible state machine q-smint o: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e & di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu pef 80902 appendix: differences between q- and t-smint?o data sheet 71 2001-11-12 figure 30 iec-t/ntc-t compatible state machine t-smint o: 4b3t awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp or ltd (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 (u0 & t12e) u2 t12s t13e ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai / ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0 synchronizing rsy u1a pef 80902 appendix: differences between q- and t-smint?o data sheet 72 2001-11-12 6.2.3 command/indication codes table 32 c/i codes code q-smint o: 2b1q t-smint o: 4b3t in out in out 0000 tim dr tim dr 0001 res ??? 0010 ???? 0011 ?? ltd ? 0100 ei1 ei1 ? rsy 0101 ssp ? ssp ? 0110 dt ? dt ? 0111 ? pu ?? 1000 ar ar ar ar 1001 ???? 1010 arl arl ? arl 1011 ???? 1100 ai ai ai ai 1101 ?? res ? 1110 ? ail ? ail 1111 di dc di dc pef 80902 appendix: differences between q- and t-smint?o data sheet 73 2001-11-12 6.3 external circuitry the external circuitry of the q- and t-smint o is equivalent; however, some external components of the u-transceiver hybrid must be dimensioned different for 2b1q and 4b3t. all information on the external circuitry is preliminary and may be changed in future documents. figure 31 external circuitry q- and t-smint o note: the necessary protection circuitry is not displayed in figure 31 . table 33 dimensions of external components component q-smint o: 2b1q t-smint o: 4b3t transformer: ratio main inductivity 1:2 14.5 mh 1:1.6 7.5 mh resistance 1.3 k ? 1.75 k ? resistance 1.0 k ? 1.0 k ? resistance 9.5 ? 25 ? capacitor c 27 nf 15 nf r ptc and r comp 2r ptc + 8r comp = 40 ? n 2 (2r comp + r b ) + r l = 20 ? loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 80902 index data sheet 74 2001-11-12 7 index a absolute maximum ratings 56 b block diagram 6 c c/i codes u-transceiver 22 d dc characteristics 57 differences between q- and t-smint 68 e external circuitry s-transceiver 52 u-transceiver 50 f features 3 i iom ? -2 interface ac characteristics 62 frame structure 14 functional description 14 l layer 1 activation / deactivation 42 loopbacks 49 led pins 9 line overload protection 56 m maintenance channel 19 o oscillator circuitry 55 p package outlines 67 pin configuration 5 pin definitions and functions 7 power consumption 59 power supply blocking 50 power-on reset 13, 65 r reset generation 13 input signal characteristics 64 power-on reset 13, 65 under voltage detection 13, 65 s s/q channels 34 scrambler / descrambler 21 s-transceiver functional description 33 state machine, nt 38 supply voltages 59 system integration 11 t test modes 10 u u-interface hybrid 50 under voltage detection 13, 65 u-transceiver 4b3t frame structure 15 functional description 15 state machine nt 23 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. ? dr. ulrich schumacher |
Price & Availability of PEF80902H
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |